The dominant source of thermal resistance for silicon photonic devices patterned on silicon on insulator (SOI) wafers is the buried oxide layer. Different devices patterned near each other in the same wafer may have different thermal needs. To ensure efficient thermally driven silicon devices there is a need for a large thermal resistance. This is in contrast to temperature sensitive components, for example lasers, that need to have low thermal resistance in order to reduce their temperature to ensure good performance. The ideal situation would be the ability to tailor the thermal resistance across the wafer or die depending on the device being fabricated.